This invention relates to bias sensing in DRAM (dynamic random access memory) sense amplifiers. More particularly, this invention relates to improving the refresh performance of DRAM devices.
As a result of charge leakage from DRAM memory cells, sense amplifier devices sense (or sample) and restore electrical charge within each of the memory cells of a given DRAM device. In order to sense and restore the electrical charge of a memory cell that is connected to a particular digit line, a sense amplifier compares the bias voltage on a xe2x80x9creferencexe2x80x9d digit line with the bias voltage on the digit line connected to the memory cell that is accessed (i.e., read).
If a logic xe2x80x9c1xe2x80x9d is stored in the accessed memory cell capacitor, upon accessing the memory cell, stored electrical charge from the capacitor is shared with the digit line. This slightly raises the voltage on the memory cell digit line relative to the reference digit line bias voltage. The sense amplifier detects this voltage change and applies a suitable voltage (e.g., Vcc) to the memory cell digit line such that the memory cell is recharged and restored to a full level of electrical charge.
If a logic xe2x80x9c0xe2x80x9d is stored in the memory cell capacitor, upon accessing the memory cell, the absence of stored electrical charge in the capacitor causes some electrical charge present on the biased digit line to be shared with the memory cell. This slightly reduces the voltage on the memory cell digit line relative to the biased reference digit line. The sense amplifier detects this voltage change and applies a ground (GND) signal to the memory cell digit line so that the accessed memory cell is fully discharged (i.e., logic xe2x80x9c0xe2x80x9d).
The refresh time or interval between sensing (i.e., reading) and restoring the electrical charge within memory cells is limited to the bias voltage level applied to the reference digit lines. For example, a DRAM memory cell holding an electrical charge representative of a logic xe2x80x9c1,xe2x80x9d is sensed after a finite time interval (refresh time). The sense amplifier then determines that a logic xe2x80x9c1xe2x80x9d is stored in the memory cell and restores its electrical charge to full value. However, if this refresh duration is too long, the electrical charge stored within this memory cell will degrade too much. When this occurs, the sense amplifier erroneously determines that a logic xe2x80x9c0xe2x80x9d is stored in the memory cell. Thus, it does not restore the memory cell electrical charge to its full value (i.e., logic xe2x80x9c1xe2x80x9d).
Therefore, for a memory cell storing a logic xe2x80x9c1,xe2x80x9d the refresh time must occur before the voltage on the sensed memory cell digit line drops below the reference digit line bias voltage. Otherwise, the DRAM device erroneously detects a logic xe2x80x9c0.xe2x80x9d To avoid this, the interval between refresh times must be reduced. However, by reducing the interval between refresh times, the power dissipation within the DRAM device undesirably increases. This becomes progressively problematic as DRAM memory arrays increase in memory capacity as their physical dimensions decrease. By reducing the reference digit line bias voltage, the time interval between the refresh operation (refresh time) increases as a result of providing an increased margin for electrical charge degradation in the memory cell.
It is known that by including dummy memory cells on the digit lines of DRAM memory devices, the bias voltage for any particular reference digit line can be reduced to improve the refresh performance. By reducing this bias voltage (threshold level), the probability of logic xe2x80x9c1xe2x80x9d detection increases (increasing reliability), and therefore, the required time between refresh operations increases.
However, the inclusion of dummy cells inefficiently uses fabrication area, which is particularly undesirable in light of the trend towards smaller DRAM array devices with increased memory capacity.
In view of the foregoing, it would be desirable to provide improved refresh performance in DRAM memory devices by varying the threshold or bias voltage used in the sensing operation.
It is an object of this invention to provide improved refresh performance in DRAM memory devices by varying the threshold or bias voltage used in the sensing operation.
In accordance with the invention, a DRAM device is provided that has a plurality of digit lines and a plurality of sense amplifiers, where each sense amplifier is coupled to an adjacent pair of digit lines. Each adjacent pair of digit lines includes a first digit line and a second digit line. The DRAM device also includes a first voltage coupling/decoupling device having an output coupled to the first digit line and a second coupling/decoupling device having an output coupled to the second digit line. The first voltage coupling device capacitively couples a voltage onto the first digit line and the second voltage coupling device capacitively decouples a second voltage from the second digit line, wherein the first digit line is an xe2x80x9cactivexe2x80x9d digit line and the second digit line is a xe2x80x9creferencexe2x80x9d digit line.
This embodiment preferably operates as follows in accordance with the invention: an electrical bias voltage is applied to the first and second digit lines. Electrical-charge within the memory cell is accessed such that electrical-charge sharing occurs between the memory cell and the first digit line, generating a first digit line bias voltage. After the memory cell is accessed, voltage is capacitively decoupled from the second digit line, causing a reduction in bias voltage. The DRAM sense amplifier is then fired in order to restore the electrical charge in the memory cell to its designated charge value (logic xe2x80x9c1xe2x80x9d or logic xe2x80x9c0xe2x80x9d).
A second embodiment of a DRAM device in accordance with the invention has first and second digit lines, first and second transistors, sense amplifiers, and first and second voltage coupling/decoupling devices. The first and second digit lines have a line connection. The first and second transistors each have a first and second terminal. The second terminal of the first transistor couples to the line connection of the first digit line, and the second terminal of the second transistor couples to the line connection of the second digit line.
Each sense amplifier has a first and second sensing connection, wherein the first sensing connection couples to the first terminal of the first transistor, and the second sensing connection couples to the first terminal of the second transistor. Each of the first and second voltage coupling/decoupling devices has an output, wherein the first coupling/decoupling device output couples to the first sensing connection and to the first terminal of the first transistor, and the second coupling/decoupling device output couples to the second sensing connection and to the first terminal of the second transistor.
This second embodiment preferably operates as follows in accordance with the invention: a voltage is applied to the first and second digit lines. Electrical-charge within the memory cell is accessed such that electrical charge sharing occurs between the memory cell and the first digit line, generating a first digit line bias voltage. After the memory cell is accessed, the first isolation transistor is switched ON so that the first sensing connection couples to the first digit line, and the second isolation transistor is switched ON so that the second sensing connection couples to the second digit line. The first and second isolation transistors are then switched OFF so that the first and second sensing connections are electrically isolated from the first and second digit lines. Following the isolation of the sense amplifier connections from the digit lines, a second voltage is capacitively decoupled from the second sense amplifier connection, thus reducing its bias voltage. The DRAM sense amplifier is then fired in order to restore the electrical charge in the memory cell to its designated charge value (logic xe2x80x9c1xe2x80x9d or logic xe2x80x9c0xe2x80x9d).